To ensure stable operation, some electronic appliances provided with a control portion such as a microcomputer, a DSP, or a logic circuit put the control portion into an unreset state and make it operate when a power supply voltage to be fed to the electronic appliance becomes a predetermined voltage or higher. On the other hand, before the power supply voltage becomes so low that the control portion or the like cannot operate, they sometimes need to perform predetermined processing such as data backup required when power supply is down. Therefore, many electronic appliances incorporate a voltage detection device that monitors a power supply voltage to be fed so as to detect that it has become a predetermined voltage. Among those voltage detection devices, there are some which are capable of delaying an output signal by a predetermined delay time after detecting that the power supply voltage has become a predetermined voltage or higher. The reason is as follows. In general, the power supply voltage to be fed continues to rise even after it has become a predetermined voltage or higher, and then becomes stable. Therefore, making the control portion of the electronic appliance operate with a delay after detecting that the power supply voltage has become a predetermined voltage is expected to offer even more stable operation of the electronic appliance.
FIG. 7 is a circuit diagram showing a conventional reset IC (semiconductor integrated circuit device) that serves as the voltage detection device described above. In FIG. 7, reference numeral 1a denotes a reset IC. The reset IC 1a includes, as its external terminals, an input terminal 2 that receives an input voltage Vin, an output terminal 3 that outputs an output signal (monitor signal) Vout indicating whether the input voltage Vin is higher or lower than a predetermined voltage, and a connection terminal CT electrically connected to one end of a capacitor C that is fitted outside the reset IC 1a. Note that the other end of the capacitor C is connected to a ground GND. In general, the input voltage Vin is a power supply voltage to be fed to an electronic appliance in which the reset IC 1a is incorporated, and the output signal Vout outputted from the output terminal 3 permits a control portion such as a microcomputer, a DSP, or a logic circuit provided inside the electronic appliance to be switched between a reset state and a non-reset state.
Inside the reset IC 1a shown in FIG. 7, a voltage division circuit 5 is connected to the input terminal 2, and an output from the voltage division circuit 5 is fed to the inverting input terminal (−) of a comparator (comparison circuit) 11. On the other hand, a reference voltage Vref from a reference voltage generation circuit 7 is fed to the non-inverting input terminal (+) of the comparator 11. The output terminal of the comparator 11 is connected to the gate of an N-channel MOS transistor (switch) 12. The drain of the MOS transistor 12 is connected to an electric power supply Vdd via a charging resistance R, and is connected to the input terminal of an amplifier 13 whose threshold voltage exhibits hysteresis. The source of the MOS transistor 12 is connected to a ground GND, and the output terminal of the amplifier 13 is connected to the output terminal 3 via buffer inverters 14 and 15.
An operation of the reset IC 1a configured as described above will be described with reference to FIG. 8. FIG. 8 is a waveform diagram showing voltage waveforms of the external terminals of the reset IC 1a, that is, from top to bottom, a voltage waveform of an input voltage Vin to be applied to the input terminal 2, a voltage waveform of a terminal voltage Vct of the connection terminal CT, and a voltage waveform of an output signal Vout from the output terminal 3. In each of the voltage waveforms, the vertical axis represents voltage, and the horizontal axis represents time. On the other hand, VDET shown in FIG. 8 denotes a reset detection voltage, and VDET+ΔVDET denotes a non-reset voltage. The reset detection voltage is a voltage at which the output signal Vout is switched from high level (hereinafter referred to as “H”) to low level (hereinafter referred to as “L”), and the non-reset voltage is a voltage at which the output signal Vout is switched from “L” to “H”. Here, ΔVDET is the difference between the reset detection voltage and the non-reset voltage, and is referred to as a hysteresis voltage. By giving a hysteresis voltage, it is possible to prevent malfunctioning that could be caused by noise or the like (within the hysteresis voltage) of the input voltage Vin. It is to be noted that the voltage division circuit 5 shown in FIG. 7 can be composed of, for example, a voltage dividing resistance that divides the input voltage Vin with a predetermined voltage ratio and a switch that is switched on/off according to an output of the comparator 11 so as to vary the voltage dividing ratio, thereby giving the hysteresis voltage ΔVDET.
First, an operation performed when the input voltage Vin is swept up will be described. As shown in FIG. 8, at time T0, the input voltage Vin starts to rise gradually, that is, to sweep up. This input voltage Vin is divided by the voltage division circuit 5 shown in FIG. 7, and the divided voltage from the voltage division circuit 5 is fed to the inverting input terminal (−) of the comparator 11. The comparator 11 compares the divided voltage with a reference voltage Vref from the reference voltage generation circuit 7. When the divided voltage is lower than the reference voltage Vref, that is, when the input voltage Vin is lower than the non-reset voltage VDET+ΔVDET, the output of the comparator 11 turns to “H”, whereby the MOS transistor 12 turns on, and the potential of the drain of the MOS transistor 12 becomes equal to the potential of the ground GND. Therefore, at this time, the capacitor C is in a discharged state, and the terminal voltage Vct of the connection terminal CT is 0 V. On the other hand, the output signal Vout takes “L” via the amplifier 13 and the inverters 14 and 15.
At time T1 at which the input voltage Vin reaches the non-reset voltage VDET+ΔVDET, the divided voltage from the voltage division circuit 5 exceeds the reference voltage Vref. As a result, the output of the comparator 11 turns to “L”, the MOS transistor 12 turns off, and thus the capacitor C starts to be charged with a charging current flowing from the electric power supply Vdd and being limited by the charging resistance R. Accordingly, the terminal voltage Vct of the connection terminal CT rises according to a time constant determined by a resistance value of the charging resistance R and the capacitance of the capacitor C.
At time T2 at which the terminal voltage Vct exceeds a threshold voltage Vth (on) of the amplifier 13, the output of the amplifier 13 is inverted from “L” to “H”, and thus the output signal Vout is switched from “L” to “H”. When the output signal Vout takes “H”, the electronic appliance in which the reset IC 1a is incorporated is unreset, and shifts into an operating state. Here, the time difference between time T1 and time T2 corresponds to a delay time TPLH with which the output signal Vout is switched from “L” to “H” when the input voltage Vin has risen, and with which the output signal Vout is shifted from “L” to “H” so as to unreset the electronic appliance and make it operate after the input voltage Vin becomes stable. This delay time TPLH can be set at an arbitrary time by replacing the capacitor C with a capacitor of different capacitance.
Next, an operation performed when the input voltage Vin is swept down will be described. As shown in FIG. 8, at time T3, the input voltage Vin starts to decrease gradually, that is, to sweep down. When the input voltage Vin is higher than the reset detection voltage VDET, the capacitor C is in a charged state, the potential of the terminal voltage Vct of the connection terminal CT becomes equal to the potential of the electric power supply Vdd, and the output signal Vout takes “H”. When the input voltage Vin is swept down from that state, and becomes lower than the reset detection voltage VDET at time T4, the divided voltage from the voltage division circuit 5 becomes lower than the reference voltage Vref. As a result, the output of the comparator 11 turns to “H”, the MOS transistor 12 turns on, and thus the capacitor C is discharged via the MOS transistor 12. Accordingly, the terminal voltage Vct of the connection terminal CT decreases according to a time constant determined by the on resistance of the MOS transistor 12 and the capacitance of the capacitor C.
At time T5 at which the terminal voltage Vct becomes lower than a threshold voltage Vth (off) of the amplifier 13, the output of the amplifier 13 is inverted from “H” to “L”, and thus the output signal Vout is switched from “H” to “L”. When the output signal Vout takes “L”, the electronic appliance in which the reset IC 1a is incorporated shifts into a reset state. This helps prevent the electronic appliance from malfunctioning or running out of control by stopping the operation thereof before such problems occur due to reduction in power supply fed to the electronic appliance. Moreover, it is possible to make the electronic appliance perform processing such as data backup required when power supply is down. Here, the time difference between time T4 and time T5 corresponds to a delay time TPHL with which the output signal Vout is switched from “H” to “L” when the input voltage Vin has dropped. When the capacitance of the capacitor C is made larger so as to make longer the delay time TPLH accompanying the rising of the input voltage Vin, the delay time TPHL accompanying the dropping of the input voltage Vin also becomes longer.
There has been proposed a reset control circuit in which two reset control circuit portions having different delay times are arranged in series or parallel, each reset control circuit portion including voltage detection means for detecting whether a voltage has risen or dropped by comparing a power supply voltage with a predetermined voltage value, signal delay means for delaying a detection signal by a predetermined delay time when the voltage detection means detects that the voltage has risen, and a reset output portion that generates a reset control signal for performing reset control of a circuit based on the detection signal delayed by the signal delay means (see, for example, Patent Publication 1).    Patent Publication 1: Japanese Patent Application Laid-Open No. H5-206811